I’m a fan of this, although I’m concerned about the security/trust model: using a third-party CI orchestrator on top of GHA means trusting them with all of your secrets, potentially sensitive logs, etc. Those concerns are somewhat lessened in the context of public repos, but even public repos contain nontrivial workflows that use configured secrets.
That has been the case so far but is changing this year.
The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months.
I mean things like the Milk-V Pioneer were already faster but expensive.
One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That and US sanctions (eg. Sophgo SG2380).
“Good enough” here was meant to mean good enough to sell more, and therefore to drop prices.
That is already happening. It just needs to happen more. And I think it will. If you don’t find the RISC-V boards of 24 months from now “good enough”, that is ok with me. I just want them to get cheaper.
The other thing that is happening on that front is that microcontrollers are getting more powerful and staying inexpensive. You can get RISC-V microcontrollers today with similar performance to the original Raspberry Pi and with things like WiFi, Bluetooth, and USB. They are crazy cheap and there are many projects for which they are now “good enough”. And, of course, they keep getting better.
Well, part of “good enough” is features. The RVA23 profile was ratified a few months ago and the first chips are appearing now. That brings RISC-V to feature parity with X86-64 and ARM, including things like vector instructions and virtualization. QUbuntu 26.04 is compiled to require RVA23. So, the RISC-V advocates got that part right. Of course, the other side of “good enough” is performance.
The SpacemiT K3 has the multi-core performance of a 2019 MacBook Air and higher AI performance than an M4. That is better multi-core than an RK3588. If it were less expensive, the K3 would already be good enough for many people.
Alibaba has the C930 which is faster than the K3. We will see if it gets released to the rest of us.
Tenstorrent will release a chip in a few months that is twice as fast as the K3.
The recently announced C950 is supposed to be even faster but will be a year or more.
Of course, “good enough” is subjective but my statement was based on the above.
But you are right that there have been some false starts.
The SG2380 was just as fast as K3 and was ready to go two years ago. TSMC refused to manufacture it over US sanctions.
Ventana was about to release a very fast RISC-V chip but Qualcomm bought them.
Rivos was very close to releasing a RISC-V GPU but Meta bought them.
But even without these high-end chips, RISC-V is enjoying great success. It is taking over the microcontroller space. And billions of RISC-V cores are shipping.
It is the case for embedded microcontrollers. An ESP32-C series is about as cheap as you can get a WiFi controller, and it includes one or more RISC-V cores that can run custom software. The Raspberry Pi Pico and Milk-V Duo are both a few dollars and include both ARM and RISC-V view. with all but the cheapest Duo able to run Linux.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough.
The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
I'd be pretty surprised if Ascalon actually hits Zen 5 perf (I'm gessing more like Zen2/3 for most real world workloads). CPU design is really hard, and no one makes a perfect CPU in their first real generation with customers. Tenstorrent has a good team, but even the "simple" things like compilers won't be ready to give them peak performance for a few years.
All RISC ISAs are basically the same thing as far as compiler optimisation is concerned, and there is 40 years of work into that already.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.
At least for SBCs, I’ve bought a few orange pi rv2s and r2s to use as builder nodes, and in some cases they are slower than the same thing running in qemu w/buildx or just qemu
The arrival of the first RVA23 chips, which is expected next month, will change the status quo.
Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are no good.
And it'll only get better from there, as other, much faster, RVA23 chips like Tenstorrent Alastor ship later this year.
Sadly still on quite old hardware, with no RVV.
Hopefully scaleway will have some newer servers in the future and this can be simply updated to the new devices.
RISE is supported by many legit companies. Stealing is for sure not the intent.
The idea is to promote testing on RISC-V and to eliminate lack of hardware for being the reason not to. Obviously, low budget projects and Open Source are the primary targets. Commercial products can afford real RISC-V hardware.
I’m a fan of this, although I’m concerned about the security/trust model: using a third-party CI orchestrator on top of GHA means trusting them with all of your secrets, potentially sensitive logs, etc. Those concerns are somewhat lessened in the context of public repos, but even public repos contain nontrivial workflows that use configured secrets.
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My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
I've added it, to one of my repos, and yes, it's slower than using emulation.
Particularly for my use case, Go cross compilation, QEMU and binfmt work really well together.
Still, for some things, it's nice to test on actual hardware.
Here's a workflow so you can see both approaches working: https://github.com/ncruces/wasm2go/blob/main/.github/workflo...
That has been the case so far but is changing this year.
The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months.
I mean things like the Milk-V Pioneer were already faster but expensive.
One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That and US sanctions (eg. Sophgo SG2380).
One thing I observed is that RVV code is usually slower in QEMU
Of course it is. Emulating parallel operations on 4 or 8 or 16 or 32 elements one at a time using scalar instructions is expected to be slow.
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase.
Performance will get “good enough” over the next 2 years. Prices will drop after that.
I should have replied differently.
“Good enough” here was meant to mean good enough to sell more, and therefore to drop prices.
That is already happening. It just needs to happen more. And I think it will. If you don’t find the RISC-V boards of 24 months from now “good enough”, that is ok with me. I just want them to get cheaper.
The other thing that is happening on that front is that microcontrollers are getting more powerful and staying inexpensive. You can get RISC-V microcontrollers today with similar performance to the original Raspberry Pi and with things like WiFi, Bluetooth, and USB. They are crazy cheap and there are many projects for which they are now “good enough”. And, of course, they keep getting better.
That the "good enough" SoCs will be arriving "over the next 2 years" is what the RISC-V advocates have told us for quite a few years now.
Well, part of “good enough” is features. The RVA23 profile was ratified a few months ago and the first chips are appearing now. That brings RISC-V to feature parity with X86-64 and ARM, including things like vector instructions and virtualization. QUbuntu 26.04 is compiled to require RVA23. So, the RISC-V advocates got that part right. Of course, the other side of “good enough” is performance.
The SpacemiT K3 has the multi-core performance of a 2019 MacBook Air and higher AI performance than an M4. That is better multi-core than an RK3588. If it were less expensive, the K3 would already be good enough for many people.
Alibaba has the C930 which is faster than the K3. We will see if it gets released to the rest of us.
Tenstorrent will release a chip in a few months that is twice as fast as the K3.
The recently announced C950 is supposed to be even faster but will be a year or more.
Of course, “good enough” is subjective but my statement was based on the above.
But you are right that there have been some false starts.
The SG2380 was just as fast as K3 and was ready to go two years ago. TSMC refused to manufacture it over US sanctions.
Ventana was about to release a very fast RISC-V chip but Qualcomm bought them.
Rivos was very close to releasing a RISC-V GPU but Meta bought them.
But even without these high-end chips, RISC-V is enjoying great success. It is taking over the microcontroller space. And billions of RISC-V cores are shipping.
which, sadly, isnt the case right now
It is the case for embedded microcontrollers. An ESP32-C series is about as cheap as you can get a WiFi controller, and it includes one or more RISC-V cores that can run custom software. The Raspberry Pi Pico and Milk-V Duo are both a few dollars and include both ARM and RISC-V view. with all but the cheapest Duo able to run Linux.
All Duos run Linux.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough.
The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
The RISC-V ISA can be fast.
Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years.
The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation).
This should give you an idea about how fast RISC-V is improving.
I'd be pretty surprised if Ascalon actually hits Zen 5 perf (I'm gessing more like Zen2/3 for most real world workloads). CPU design is really hard, and no one makes a perfect CPU in their first real generation with customers. Tenstorrent has a good team, but even the "simple" things like compilers won't be ready to give them peak performance for a few years.
All RISC ISAs are basically the same thing as far as compiler optimisation is concerned, and there is 40 years of work into that already.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.
>I'd be pretty surprised if Ascalon actually hits Zen 5 perf
Certainly not in the Atlantis SoC, due to the older fab node used. Zen2-3 territory IPC is the expectation, with lower clocks than these actually got.
By the time they have the necessary scale to use the best fabs, they'll be tapping out something newer than the Ascalon that went into Atlantis.
Tenstorrent expects to reach parity with the best x86 and arm chips by 2028.
Assuming AMD, Intel, ARM, Apple in a few years haven't released new CPUs, otherwise the difference is the same as today.
Same experience here.
At least for SBCs, I’ve bought a few orange pi rv2s and r2s to use as builder nodes, and in some cases they are slower than the same thing running in qemu w/buildx or just qemu
The arrival of the first RVA23 chips, which is expected next month, will change the status quo.
Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are no good.
And it'll only get better from there, as other, much faster, RVA23 chips like Tenstorrent Alastor ship later this year.
s/Alastor/Atlantis/g.
Alastor is something else; a core from Tenstorrent that is considerably smaller than Ascalon.
Sadly still on quite old hardware, with no RVV. Hopefully scaleway will have some newer servers in the future and this can be simply updated to the new devices.
You can get RVV instances from Saleway.
Oh, cool, I didn't see them on the website. (https://labs.scaleway.com/en/em-rv1/)
Very good move. Hopefully GitHub won't ruin this with their CI charging changes.
GitHub only :(
..is this RVA23?
Not yet
RV64GC (C910 cores)
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Perfect for snooping on other people’s projects. No one in their right mind would touch this. It’s cheaper to buy the board yourself.
Yes, what a devious plan: give open source software projects a free CI service so you can... read their open source software code?
diabolical
devious
duplicitous
dastardly
It seems to be a Linux Foundation project, my trust is implicit higher than what you're claiming. Why wouldn't you trust them?
It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
Why would you trust anyone offering free candies?
Depends on the context. I'd trust the lady giving free candy samples in a candy store. The incentive is clear here, too: RISC-V needs adoption.
RISE is supported by many legit companies. Stealing is for sure not the intent.
The idea is to promote testing on RISC-V and to eliminate lack of hardware for being the reason not to. Obviously, low budget projects and Open Source are the primary targets. Commercial products can afford real RISC-V hardware.
This is who you are trusting: https://riseproject.dev/members/
people better not be snooping on my public open source projects!