Cool, I thought this was a CPU custom designed for Doom, but I guess that's just a 486 :)
edit: I went to down a quick hole "The historical footnote is that a version of this genuinely happened. SNES Doom shipped with a Super FX 2 in the cartridge, a custom RISC chip with a pixel-plot instruction, because the console's own CPU had no chance. Jaguar and PlayStation ports both moved the rasteriser onto dedicated hardware. Doom's design was shaped by the absence of an FPU, and then hardware kept getting built to catch up with it."
This reminded me of a project I built a while back: a RV32IM emulator in C++ that can boot and run DOOM. Initially I implemented only RV32I, and implementing the M extension provided a massive speedup!
Hi, I didn't follow any specific guide on this, but asked ChatGPT about the bare minimum environment needed to run DOOM. From there, I figured out how to execute the instructions using a switch-case and how to make a custom syscall to trigger rendering.
If you don't want to delegate the fun of learning to an LLM, here's how I've built a RV64IM simulator in C in a weekend. All you need is an opcode table, the RISC-V specs and to implement each instruction; the good thing of RISC CPUs is that instructions are very simple (i.e. pretty much everything is a variation of `dest = src1 OP src2`) and memory instructions are dedicated. The other cool thing is that there are no "flags". Start with the base instruction set, then you can add M on top later. 64-bit support requires just a handful more instructions to zero/sign extend from 32-bit.
Then, wire your simulator to https://github.com/riscv-software-src/riscv-tests, and there you have an official test suite. When everything passes, you have a fully-compliant RISC-V CPU. You can at this point tell GCC or Rust or your favourite language to compile to RV32IM and see it run on your simulator. It's a very gratifying process.
If you get at this stage, you might want to use the ecall instruction to hard-code I/O operations such as "read from stdin" or "print a character", and there you have a sandboxed CPU that you can target with your favourite programming language. Make it run DOOM (start with https://github.com/ozkl/doomgeneric and see which I/O do you need), or turn it into a toy game console; the sky's the limit.
---
Here's a copy-paste of the list of resources I have saved in my notes:
I just did the same thing, but for a byte-code interpreter for a completely novel ISA I made up a while back (with an assist from Claude). I just haven't made the HN post yet, since I'm doing a bit of cleanup.
For anyone else curious: custom FPGA-based CPU code but not a custom architecture. This is an RV32I core. The article takes along time to give up this fact.
Deciding on an ISA like RV32I only sets constraints on your architecture, it doesn't give you any of it for free. So I think it's entirely valid to say that it's a custom architecture if they didn't use any pre-existing CPU design.
Basically, they had the API interface and implemented everything behind it. I think saying that "it's an RV32I core" vastly underrates the design work that goes into actually implementing an RV32I core from scratch.
Making a particularly good core is hard. Making a core to the minimum risc-v spec is what you do in a single college course. It's what the ISA was designed for.
It's common to call the instruction set just "architecture", or ISA (instruction set architecture) to be more precise. The implementation is commonly called "microarchitecture".
RV32I doesn't define any architecture, it's just an ISA i.e. a software contract that happens to be implementable in hardware. The CPU could run on outer space goop and still be RV32I.
The *architecture* is RV32I_Zmmul which is unambiguously neither new nor custom.
What you describe (the specific implementation details of a core) is *microarchitecture*. In this case clearly a lot of work was done and it is cool, but the *architecture* is indeed RV32I and not custom
I was not undermining anything. I was helping others find the info I sought and took a while to find. This is why i left my comment. Everyone has their own interests. As an example, my thoughts were "whoa... a new architecture... did they write a new compiler or rewrite doom in assembly?" and for that "it is rv32i" would have been a quick answer.
Cool, I thought this was a CPU custom designed for Doom, but I guess that's just a 486 :)
edit: I went to down a quick hole "The historical footnote is that a version of this genuinely happened. SNES Doom shipped with a Super FX 2 in the cartridge, a custom RISC chip with a pixel-plot instruction, because the console's own CPU had no chance. Jaguar and PlayStation ports both moved the rasteriser onto dedicated hardware. Doom's design was shaped by the absence of an FPU, and then hardware kept getting built to catch up with it."
Reading "Custom CPU" I expected wafer.space, instead of FPGA.
https://www.linkedin.com/posts/hirosh-dabui-a5367443_linux-r...
Great work!
This reminded me of a project I built a while back: a RV32IM emulator in C++ that can boot and run DOOM. Initially I implemented only RV32I, and implementing the M extension provided a massive speedup!
If anyone's curious, here's the source code: https://github.com/lalitshankarch/rvcore
Nice one! Sounds like a fun project to do. Did you follow any tutorial or guide for this? If so, I would appreciate it if you shared it.
Hi, I didn't follow any specific guide on this, but asked ChatGPT about the bare minimum environment needed to run DOOM. From there, I figured out how to execute the instructions using a switch-case and how to make a custom syscall to trigger rendering.
I made a post a while back that details the entire process: https://www.reddit.com/r/EmuDev/comments/1t1or4j/doom_runs_o...
Thanks, am going to check it out.
If you don't want to delegate the fun of learning to an LLM, here's how I've built a RV64IM simulator in C in a weekend. All you need is an opcode table, the RISC-V specs and to implement each instruction; the good thing of RISC CPUs is that instructions are very simple (i.e. pretty much everything is a variation of `dest = src1 OP src2`) and memory instructions are dedicated. The other cool thing is that there are no "flags". Start with the base instruction set, then you can add M on top later. 64-bit support requires just a handful more instructions to zero/sign extend from 32-bit.
Then, wire your simulator to https://github.com/riscv-software-src/riscv-tests, and there you have an official test suite. When everything passes, you have a fully-compliant RISC-V CPU. You can at this point tell GCC or Rust or your favourite language to compile to RV32IM and see it run on your simulator. It's a very gratifying process.
If you get at this stage, you might want to use the ecall instruction to hard-code I/O operations such as "read from stdin" or "print a character", and there you have a sandboxed CPU that you can target with your favourite programming language. Make it run DOOM (start with https://github.com/ozkl/doomgeneric and see which I/O do you need), or turn it into a toy game console; the sky's the limit.
---
Here's a copy-paste of the list of resources I have saved in my notes:
- https://github.com/libriscv/libriscv A very fast RISC-V VM with sandboxing of memory and syscalls.
- https://luplab.gitlab.io/rvcodecjs/ RISC-V Instruction Encoder/Decoder
- https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/noteboo... Reference card
- https://cs.brown.edu/courses/csci1952y/2024/assets/docs/risc... Spec
- https://riscv-software-src.github.io/riscv-unified-db/manual...
- ABI: https://lists.riscv.org/g/tech-psabi/attachment/61/0/riscv-a...
Good luck!
Huge thanks! Will certainly try doing that.
Very cool!
I just did the same thing, but for a byte-code interpreter for a completely novel ISA I made up a while back (with an assist from Claude). I just haven't made the HN post yet, since I'm doing a bit of cleanup.
https://github.com/paulmooreparks/Maize/ https://paulmooreparks.github.io/Maize/
For anyone else curious: custom FPGA-based CPU code but not a custom architecture. This is an RV32I core. The article takes along time to give up this fact.
Deciding on an ISA like RV32I only sets constraints on your architecture, it doesn't give you any of it for free. So I think it's entirely valid to say that it's a custom architecture if they didn't use any pre-existing CPU design.
Basically, they had the API interface and implemented everything behind it. I think saying that "it's an RV32I core" vastly underrates the design work that goes into actually implementing an RV32I core from scratch.
Making a particularly good core is hard. Making a core to the minimum risc-v spec is what you do in a single college course. It's what the ISA was designed for.
It's a custom implementation of an existing architecture
It's common to call the instruction set just "architecture", or ISA (instruction set architecture) to be more precise. The implementation is commonly called "microarchitecture".
RV32I doesn't define any architecture, it's just an ISA i.e. a software contract that happens to be implementable in hardware. The CPU could run on outer space goop and still be RV32I.
The *architecture* is RV32I_Zmmul which is unambiguously neither new nor custom.
What you describe (the specific implementation details of a core) is *microarchitecture*. In this case clearly a lot of work was done and it is cool, but the *architecture* is indeed RV32I and not custom
I was not undermining anything. I was helping others find the info I sought and took a while to find. This is why i left my comment. Everyone has their own interests. As an example, my thoughts were "whoa... a new architecture... did they write a new compiler or rewrite doom in assembly?" and for that "it is rv32i" would have been a quick answer.
thanks for saving me the time but it is pretty cool to see i'd love to learn more about fpga my goal is to run very old rare consoles
why Zmmul and not full M — is it just fpga area, or did the doom port let you drop div/rem?
Always a delight seeing Chisel in the wild :)