Obviously vibecoded but interesting nevertheless. The agent left everything marked as untested in the README but the output snippets toward the bottom imply that it got something working enough to log in and run some commands.
Nobody is going to mistake this for a carefully crafted port of Linux but it at least serves as a proof of concept.
The real downside of the vibecoding is that we don’t get any helpful information about what it took to get it done with thoughtful analysis from a human. Just a chunk of code in a GitHub repo with some half-coherent README. There’s a docs folder, but the documentation about the MMU part just says that there are two MMUs across a couple lines of notes. Okay, great.
What I remember was they said it could come back if people needed it but it was broken for looking (months, years) at a time. So even if they didn't remove it, 6.12 might be the last working version with it anyway
Thanks for the links. This doesn't seem to be a true RISC-V MMU (according to the Sv32 specification) integrated into the CPU core itself, but just a peripheral designed for memory mapped SPI flash and PSRAM. So as far as I understand there is no true process isolation with page faults and dynamic paging.
The Microchip PIC32MZ MCU has an MMU as well. But not with wireless options in a 8x8 QFN80 package like this ESP32-S31. That's pretty small. No flash though.
Obviously vibecoded but interesting nevertheless. The agent left everything marked as untested in the README but the output snippets toward the bottom imply that it got something working enough to log in and run some commands.
Nobody is going to mistake this for a carefully crafted port of Linux but it at least serves as a proof of concept.
The real downside of the vibecoding is that we don’t get any helpful information about what it took to get it done with thoughtful analysis from a human. Just a chunk of code in a GitHub repo with some half-coherent README. There’s a docs folder, but the documentation about the MMU part just says that there are two MMUs across a couple lines of notes. Okay, great.
Everything is untested or WIP. What is the news here, sorry?
The news is: vibe coder vibe coded this and got their agents to upvote it.
his*
Is that a critical correction? Is a gender neutral pronoun somehow unacceptable?
> In mainline linux, XIP support on RISC-V was removed, so 6.12 was used instead which has proper XIP support.
Doesn't that put it in an awkward position relying on a dead end feature?
What I remember was they said it could come back if people needed it but it was broken for looking (months, years) at a time. So even if they didn't remove it, 6.12 might be the last working version with it anyway
Looks interesting but wouldn't something like netBSD be a better fit?
How can it run when there is no MMU? Isn't this like rewriting a large part of the kernel?
This is for the recently released ESP32-S31 which does have a MMU, unlike the ESP32-S3.
The author has more details in this reddit post: https://eddrit.com/r/esp32/comments/1vait52/mmu_linux_on_the... And the docs section of the repo: https://github.com/GrieferPig/esp32-s31-linux/tree/main/docs...
Thanks for the links. This doesn't seem to be a true RISC-V MMU (according to the Sv32 specification) integrated into the CPU core itself, but just a peripheral designed for memory mapped SPI flash and PSRAM. So as far as I understand there is no true process isolation with page faults and dynamic paging.
The Microchip PIC32MZ MCU has an MMU as well. But not with wireless options in a 8x8 QFN80 package like this ESP32-S31. That's pretty small. No flash though.
There is actually precedent for nommu Linux, though it obviously has tradeoffs.
Have a try.